1. Field of the Invention
The present invention generally relates to a ferroelectric memory and a method of reading out data from the ferroelectric memory, and more particularly, to a ferroelectric memory having memory cells in which ferroelectric capacitors formed by ferroelectric substances such as Pb(Zr, Ti)O3 are used as storage mediums.
The present invention is also directed to a ferroelectric memory and a method of reading out data from the ferroelectric memory so as to carry out a stable reading-out operation by increasing a signal margin for reading out the data.
2. Description of the Related Art
A semiconductor memory using ferroelectric capacitors formed by ferroelectric substances such as Pb(Zr, Ti)O3 is a non-volatile memory and has a feature of having substantially the same writing-and-reading speed as that of a DRAM. Therefore, it is assumed that a demand for a large number of ferroelectric memories will increase in the future.
With respect to an operation method of the ferroelectric memory, several kinds of methods are known, and these operation methods are disclosed, for example, in U.S. Pat. No. 4,873,664 (Ramtron), and Japanese Patent Publication 7-13877 (Toshiba CO. LTD). In theses methods, by applying a voltage to the ferroelectric capacitor, the data is discriminated according to an inversion of a polarization of the ferroelectric capacitor.
When a memory cell is constructed with one transistor and one capacitor, in order to determine whether or not the polarization is inverted, a reference circuit (dummy cell) generating an intermediate load (or voltage) needs to be constructed with the ferroelectric capacitor.
However, characteristics of this reference circuit may be easily varied by process dispersion of a ferroelectric film and fatigue due to inversion (referred to as inversion fatigue, hereinafter) of the ferroelectric capacitor. Therefore, there is a problem in that the signal margin is reduced, and a stable reading-out operation may not be conducted.
In the following, a more detailed description will be given of the operation of the above-discussed prior-art ferroelectric memory.
FIG. 1 shows a schematic diagram for illustrating a part of one embodiment of a prior-art ferroelectric memory. The ferroelectric memory shown in FIG. 1 includes memory cells 1, 2, which have ferroelectric capacitors 3, 4, and transistors 5, 6 forming transmission gates. The transistors 5, 6 are so-called cell transistors.
In FIG. 1, symbols xe2x80x9cWL0 and WL1xe2x80x9d indicate word lines for selecting a memory cell, and the symbols xe2x80x9cPL0 and PL1xe2x80x9d indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected memory cell.
The ferroelectric memory shown in FIG. 1 further includes dummy cells 7, 8 which have ferroelectric capacitors 9, 10 having an overlapped area of opposite electrodes half that of the ferroelectric capacitors 3, 4, and cell transistors 11, 12. In this embodiment, into the ferroelectric capacitors 9, 10, a logic xe2x80x9c1xe2x80x9d is written.
In FIG. 1, symbols xe2x80x9cDWL0 and DWL1xe2x80x9d indicate word lines for selecting the dummy cell, and the symbols xe2x80x9cDPL0 and DPL1xe2x80x9d indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected dummy cell.
Further, symbols xe2x80x9cBL and /BLxe2x80x9d indicate bit lines forming data lines (data transmission lines), and the ferroelectric memory further includes a sense amplifier which amplifies a voltage difference between the bit lines BL and /BL when data is read out, and detects data read out from the selected memory cell.
FIG. 2 and FIG. 3 show illustrations for explaining a data-writing sequence in the memory cell of the ferroelectric memory. In these drawings, an example of the data-writing sequence in the memory cell 1 is shown. A horizontal axis indicates a voltage between the bit line BL and the plate line PL0, namely, a voltage VBL of the bit line BL to an earth ground minus a voltage VPL0 of the plate line PL0 to the earth ground. A vertical axis indicates a polarization P of the ferroelectric capacitor 3.
For example, when a logic xe2x80x9c1xe2x80x9d is written into the memory cell 1, the voltage VPL0 of the plate line PL0 is set to 0 V, and the cell transistor 5 is set to be conductive. Under this condition, the voltage VBL of the bit line BL is changed from 0 V to VCC, and is subsequently changed to 0 V.
In the above sequence, a state of the polarization P of the ferroelectric capacitor 3 changes, as shown in FIG. 2, from a point a to a point b, and then to a point c. At the point c, the polarization P of the ferroelectric capacitor 3 becomes a positive polarization Ps. As a result, a logic xe2x80x9c1xe2x80x9d is stored in the ferroelectric capacitor 3. A closed curved line of b to c to d to e to b indicates a hysteresis loop.
On the other hand, when a logic xe2x80x9c0xe2x80x9d is written into the memory cell 1, the voltage VBL of the bit line BL is set to 0 V, and the cell transistor 5 is set conductive. Under this condition, the voltage VPL0 of the plate line PL0 is changed from 0 V to VCC, and is further changed to 0 V.
In the above sequence, a voltage of a storage electrode 3A to that of a plate electrode 3B of the ferroelectric capacitor 3 changes from 0 V to xe2x88x92VCC, and is further changed to 0 V. A state of the polarization P of the ferroelectric capacitor 3 changes, as shown in FIG. 3, from a point a to a point d, and then to a point e. At the point e, the polarization P of the ferroelectric capacitor 3 becomes a negative polarization xe2x88x92Ps. As a result, a logic xe2x80x9c0xe2x80x9d is stored in the ferroelectric capacitor 3.
FIG. 4 shows waveforms for explaining a data-reading sequence from the memory cell of the ferroelectric memory. In the drawing, an example of the data-reading sequence from the memory cell 1 is shown. A waveform A indicates a variation of the voltage of the word lines WL0, DWL0, a waveform B indicates a variation of the voltage of the plate lines PL0, DPL0, and a waveform C indicates a variation of the voltage of the bit line BL. FIG. 5 shows an illustration for explaining the data-reading sequence from the memory cell of the ferroelectric memory.
When data is read out from the memory cell 1, the bit lines BL, /BL are set to 0 V, and the word lines WL0, DWL0 are increased to VCC+VTH (a threshold voltage of the cell transistor) so as to set the cell transistors 5, 11 conductive. Further, the plate lines PL0, DPL0 are increased to VCC.
At this time, for example, when the logic xe2x80x9c1xe2x80x9d is previously written in the ferroelectric capacitor 3, the polarization P of the ferroelectric capacitor 3, as shown in FIG. 5, changes from a point c to a point K1. In this case, a charge xcex4Q1, by which the voltage VBL of the bit line BL is the same as the voltage of the storage electrode 3A of the ferroelectric capacitor 3, is provided from the ferroelectric capacitor 3 to the bit line BL. As a result, the voltage VBL of the bit line BL increases from 0 V to V1 V as shown in FIG. 4.
On the other hand, for example, when the logic xe2x80x9c0xe2x80x9d is previously written in the ferroelectric capacitor 3, the polarization P of the ferroelectric capacitor 3, as shown in FIG. 5, changes from a point e to a point K2. In this case, a charge xcex4Q2, by which the voltage VBL of the bit line BL is the same as the voltage of the storage electrode 3A of the ferroelectric capacitor 3, is provided from the ferroelectric capacitor 3 to the bit line BL. As a result, the voltage VBL of the bit line BL increases from 0 V to V2 V shown in FIG. 4.
Since the overlapped area of the opposite electrodes of the ferroelectric capacitor 9 in the dummy cell 7 is half that of the ferroelectric capacitor 3 in the memory cell 1, and the logic xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor 9 in an initial condition, the voltage V/BL of the bit line /BL becomes an intermediate level between V1 and V2. This intermediate voltage may be the reference voltage (operable as a function of the dummy cell).
Therefore, when the logic xe2x80x9c1xe2x80x9d is previously written in the ferroelectric capacitor 3, since the voltage VBL (=V1) of the bit line BL is larger than the voltage V/BL of the bit line /BL, the sense amplifier 13 increases the voltage VBL of the bit line BL to the voltage VCC, and decreases the voltage V/BL of the bit line /BL to 0 V.
On the contrary, when the logic xe2x80x9c0xe2x80x9d is previously written in the ferroelectric capacitor 3, since the voltage VBL (=V2) of the bit line BL is smaller than the voltage V/BL of the bit line /BL, the sense amplifier 13 decreases the voltage VBL of the bit line BL to 0 V, and increases the voltage V/BL of the bit line /BL to the voltage VCC.
In this way, the dummy cell 7 is used for the reference voltage of all of the memory cells connected to the bit line. Therefore, in the above-discussed ferroelectric memory, the dummy cell 7 is driven every time when any memory cell connected to the bit line BL, for example, the memory cell 1, is selected. The dummy cell 8 is driven every time when any memory cell connected to the bit line /BL, for example, the memory cell 2, is selected.
Therefore, fatigue due to inversion (referred to as inversion fatigue, hereinafter) of the ferroelectric capacitors 9, 10 of the dummy cells 7, 8 increases as compared to the ferroelectric capacitors of the normal memory cell such as ferroelectric capacitors 3, 4. In this way, characteristics of the memory cell changes, and, thus, a reading-out margin decreases.
It is difficult to design the dummy cells taking into account the characteristics change due to the inversion fatigue. Therefore, there is a problem in that the prior-art ferroelectric memory shown in FIG. 1 may not stably operate for a long term.
There is another ferroelectric memory, in which the overlapped area of the opposite electrodes of the ferroelectric capacitors 9, 10 is twice that of the memory cells 3, 4, and a logic xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitors 9, 10. However, this ferroelectric memory also has the same problem as that of the ferroelectric memory shown in FIG. 1.
Next, a description will be given of an operating method of the ferroelectric memory disclosed in the above-mentioned Japanese Patent Publication No. 7-13877. This ferroelectric memory is also disclosed in xe2x80x9cProposal of an operation method of a non-volatile ferroelectric memory having a Vcc/2 common platexe2x80x9d, proceedings of EIC Electronics Society, C-509, 1995, in Japanese.
The proposed ferroelectric memory has a cell structure similar to a DRAM using the ferroelectric film for a capacitor. The ferroelectric memory is operative in a DRAM mode at a normal operation state, stores information by remanent polarization of the ferroelectric capacitor at a power-off state, and reads the information when the power source is supplied. Therefore, the ferroelectric memory is operable as a non-volatile memory.
In the following, a detailed description will be given of the above-discussed ferroelectric memory.
When the ferroelectric memory is operating in the DRAM mode, data is not stored by the remanent polarization of the capacitor, but is stored by a charge stored in linear capacitance. At this time a plate voltage level is set to a Vcc/2 voltage, and a voltage level of a storage node is set to Vcc or 0 V according to the data. In this case, when the ferroelectric memory operates in the DRAM mode, a refresh operation is required.
Subsequently, when the power source is turned off, the data is held as the remanent polarization of the ferroelectric capacitor.
Further, when the power source is supplied, the remanent polarization is changed to a storage charge. Therefore, after a reading operation is carried out in all memory cells in an FRAM mode, the memory is set to be the DRAM mode.
In this case, the plate voltage level is set to a Vcc/2 voltage, and the bit line is precharged to be 0 V. Further, a word line is selected, and a voltage level of the selected word line is increased. When the bit line is connected to the capacitor, the voltage level of the bit line increases over 0 V. However, since a degree of the increase varies according to a direction of polarization inversion, the data may be discriminated by the variance. In this way, after the data in all memory cells is read out, the ferroelectric memory is set to be the DRAM mode.
However, there is also a problem in the ferroelectric memory disclosed in Japanese Patent Publication No. 7-13877. Different from the Ramtron method, when the data is read from the ferroelectric memory, the plate line is not driven, but the voltage level of the bit line is varied. In this case, in order to discriminate whether the polarization inversion occurs, the dummy cell for generating the reference voltage is required.
Therefore, characteristics of the dummy cell influences on a reliability of the reading operation. Particularly, since a voltage applied to the capacitor is relatively small, i.e., Vcc/2, for compatibility with the DRAM mode, a signal voltage decreases, and, thus, there is a problem in that a reading error may easily occur.
It is an object of the present invention to provide a ferroelectric memory and a method of reading data from the ferroelectric memory. The ferroelectric memory does not need a dummy cell which is used for detecting data read out from a memory cell in a prior-art ferroelectric memory. Also, a stable operation of the ferroelectric memory can be carried out for a long term.
It is another object of the present invention to provide a ferroelectric memory using a dummy cell and a method of reading data from the ferroelectric memory using the dummy cell. Even in the ferroelectric memory using the dummy cell, fatigue of the dummy cell may be reduced, and a stable operation for a long term cell can be achieved.
This permits the disadvantages described above to be eliminated.
The object described above is achieved by a method of reading data from a ferroelectric memory having a memory cell which uses a ferroelectric capacitor as a storage medium, the method comprising the steps of: (a) successively applying first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields; and (b) reading out the data stored in the memory cell by detecting a variation of the polarization of the ferroelectric capacitor.
The object described above is also achieved by a method of reading data from a ferroelectric memory having a memory cell, the memory cell including a transmission gate having a first charge input-and-output port connected to a data line and a second charge input-and-output port, and a ferroelectric capacitor having a first electrode connected to the second charge input-and-output port and a second electrode connected to a driving voltage line, the method comprising the steps of: (a) controlling the transmission gate to be non-conductive; (b) precharging the data line; (c) controlling the transmission gate to be conductive; (d) applying a driving voltage to the second electrode of the ferroelectric capacitor through the driving voltage line to successively apply first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields; and (e) reading out the data stored in the memory cell to the data line.
According to the above-mentioned method of reading the data in the ferroelectric memory, the data read out from the memory cell may be detected in the same way as that of, for example, a dynamic random access memory (DRAM) using a method of precharging the bit line to a voltage VCC(power-source voltage)/2. Therefore, the method according to the present invention does not need a dummy cell.
The object described above is also achieved by a ferroelectric memory comprising a memory cell which uses a ferroelectric capacitor as a storage medium, the memory cell having: an applying part for applying first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields; and a reading part for reading out data stored in the memory cell by detecting a variation of the polarization of the ferroelectric capacitor.
The object described above is also achieved by a ferroelectric memory comprising: a memory cell including: a transmission gate having a first charge input-and-output port connected to a data line and a second charge input-and-output port; and a ferroelectric capacitor having a first electrode connected to the second charge input-and-output port and a second electrode connected to a driving voltage line; a precharging part for precharging the data line; and a driving-voltage applying part for applying a driving voltage to the second electrode of the ferroelectric capacitor through the driving voltage line to successively apply first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields, and a driving-voltage applying operation of the driving-voltage applying part is carried out after processes in which the transmission gate is controlled to be non-conductive, the data line is precharged by the precharging part, and the transmission gate is controlled to be conductive; wherein data stored in the memory cell is read out to the data line by successively applying the first and second electric fields to the ferroelectric capacitor after the processes in which the transmission gate is controlled to be non-conductive, the data line is precharged, and the transmission gate is controlled to be conductive.
According to the above-mentioned ferroelectric memory, the data read out from the memory cell may be detected in the same way as that of, for example, the DRAM using the method of precharging the bit line to the voltage VCC/2. Therefore, the ferroelectric memory according to the present invention does not need the dummy cell.
The object described above is also achieved by the method discussed above and the ferroelectric memory discussed above, wherein the data line has parasitic capacitance CBL, the parasitic capacitance CBL being set to be equal to or less than a value CBL in which a voltage difference generated in the data line when a logic xe2x80x9c1xe2x80x9d and a logic xe2x80x9c0xe2x80x9d are read out is substantially maximized.
The object described above is also achieved by the method discussed above and the ferroelectric memory discussed above, wherein one of the first and second electric fields is larger than an internal power-supply voltage, and when the data is read out, a voltage generated in the data line increases when compared with a case where the one of the first and second electric fields is substantially the same as the internal power-supply voltage.
According to the above-mentioned ferroelectric memory, the ratio of the capacitance in the bit-line and the capacitance of the ferroelectric capacitor is properly adjusted, and the driving voltage of the plate line is increased more than the power-supply voltage so as to generate a larger reading-out signal in the bit line. Therefore, a memory device operable in a stable condition for a long term may be provided.
The object described above is also achieved by a method of reading data from a ferroelectric memory having a memory cell which uses a ferroelectric capacitor as a storage medium and a dummy cell which uses a ferroelectric capacitor, wherein the data is written in the ferroelectric memory by means of a direction of the ferroelectric capacitor in the memory cell, the method comprising the steps of: (a) precharging data lines at ground level; (b) applying a first driving voltage to the ferroelectric capacitor in the memory cell; (c) generating one of first and second voltages to a data line according to the data stored in the memory cell; (d) applying a second driving voltage less than the first driving voltage to the ferroelectric capacitor in the dummy cell to generate a reference voltage; and (e) discriminating the first and second voltages generated in the step (c) based on the reference voltage to read out the data.
The object described above is also achieved by a ferroelectric memory having a memory cell which uses a ferroelectric capacitor as a storage medium and a dummy cell which uses a ferroelectric capacitor, wherein the data is written in the ferroelectric memory according to a direction of the ferroelectric capacitor in the memory cell, and when the data is read out, one of first and second voltages is provided to a data line by means of the data, the ferroelectric memory comprising: a first circuit for applying a first driving voltage to the ferroelectric capacitor in the memory cell; a second circuit for applying a second driving voltage less than the first driving voltage to the ferroelectric capacitor in the dummy cell to generate a reference voltage; and a third circuit for discriminating the first and second voltages provided when the data is read out, based on the reference voltage to read out the data.
According to the above-mentioned ferroelectric memory using the dummy cell according to the present invention, the driving voltage of the ferroelectric capacitor in the dummy cell is set to be lower than that of the ferroelectric capacitor in the memory cell. Therefore, inversion fatigue of the dummy cell is reduced, and, thus, a stable, long term data writing-in-and-reading-out operation may be expected.
The object described above is also achieved by a method of reading data from a non-volatile ferroelectric memory having a ferroelectric capacitor, the non-volatile ferroelectric memory is substantially operative in a DRAM mode at a normal operation time and holds data by remanent polarization of the ferroelectric capacitor at a power-off state, the method comprising the steps of: (a) setting voltage levels of a plate electrode and a bit line to be substantially half of a power source voltage (Vcc) when a power source is supplied; and (b) successively applying to the voltage level of the plate electrode Vcc/2xe2x86x92(Vcc/2Vxcex1)xe2x86x92(Vccxe2x88x92Vxcex2)xe2x86x92Vcc/2, where Vxcex1 and Vxcex2 are respectively first and second given voltage; wherein when the power source is supplied, a storage state of the data in all memory cells is changed from the remanent polarization to a storage charge holding information in the DRAM mode.
The object described above is also achieved by a non-volatile ferroelectric memory having a ferroelectric capacitor, the non-volatile ferroelectric memory is substantially operative in a DRAM mode at a normal operation time and holds data by remanent polarization of the ferroelectric capacitor at a power-off state, the memory comprising: a first voltage setting part for setting voltage levels of a plate electrode and a bit line to be substantially half of a power source voltage (Vcc) when a power source is supplied; and a second voltage setting part for successively applying to the voltage level of the plate electrode Vcc/2xe2x86x92(Vcc/2+Vxcex1)xe2x86x92(Vccxe2x88x92Vxcex2)xe2x86x92Vcc/2, where Vxcex1 and Vxcex2 are respectively first and second given voltage; wherein when the power source is supplied, a storage state of the data in all memory cells is changed from the remanent polarization to a storage charge holding information in the DRAM mode.
According to the above-mentioned method of reading data from the non-volatile ferroelectric memory and the non-volatile ferroelectric memory according to the present invention, when the power source is supplied, the remanent polarization of the all memory cells is changed to the storage charge, and, thus, a data recall operation is carried out. Therefore, regardless of characteristics of the dummy cell, a stable data reading-and-rewriting operation may be carried out.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.